Title :
Iterative convergence of optimal wire sizing and available buffer insertion for zero-skew clock tree optimization
Author :
Yan, Jin-Tai ; Wu, Chia-Wei ; Lin, Kai-Ping ; Lee, Yu-Cheng ; Wang, Tzu-Ya
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Chung Hua Univ., Hsinchu
Abstract :
In this paper, based on the topology of one DME-based zero-skew clock tree, the analysis of the optimal width of one wire segment and the information of available buffers on one wire segment, an iterative convergence-based algorithm is proposed to assign the optimal width and insert available buffers onto any wire segment to reduce the clock delay. The experimental results show that our proposed OWSABI algorithm reduces 78%~88% clock delay and 20%~28% total load capacitance in one DME-based zero-skew clock routing tree
Keywords :
circuit optimisation; convergence of numerical methods; interconnections; iterative methods; logic circuits; network topology; timing jitter; trees (electrical); OWSABI algorithm; available buffer insertion; clock delay; iterative convergence; load capacitance; optimal wire sizing; topology; wire segment; zero-skew clock routing tree; zero-skew clock tree optimization; Algorithm design and analysis; Capacitance; Clocks; Convergence; Delay; Information analysis; Iterative algorithms; Routing; Topology; Wire;
Conference_Titel :
Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on
Conference_Location :
Tainan
Print_ISBN :
0-7803-8660-4
DOI :
10.1109/APCCAS.2004.1412815
