High speed signal sampler by multiple-path algorithm

The proposed multi-pass algorithm is used to enhance the apparent conversion rate despite of the relatively low real-time sampling rate of the original A/D converter. Except a simple RC average circuit for delta-sigma D/A conversion and a comparator with sampling/hold for A/D conversion, the whole system is built in a single FPGA chip, including the DOS-type AWG, delta-sigma D/A converter, SAR A/D converter, TDC module, ADPLL module, DLL phase/time shifter, and data memory controller. This all digital-type design can be implemented into an ASIC or SoRC chip, and utilized as an economic and effective method to capture high bandwidth periodic signals.