DocumentCode
430991
Title
Exploring design space of scalable per-address branch predictors
Author
Kongmunvattana, Angkul ; Tiamkaew, Ekkasit
Author_Institution
Dept. of Comput. Sci. & Eng., Nevada Univ., Reno, NV, USA
Volume
B
fYear
2004
fDate
21-24 Nov. 2004
Firstpage
156
Abstract
While a scalable per-address (SPA) branch predictor reduces the cost of implementing per-address two-level branch predictors by about 50% through the exploitation of value locality in the history of branch outcomes, it suffers from internal conflict within the pattern history table (PHT), called pattern aliasing or interference. In this paper, we propose and evaluate alternative designs of SPA predictor to reduce aliasing or interference rate in its PHT as well as to improve its prediction accuracy. Several PHT designs are evaluated against a direct-mapped PHT used in the original SPA branch predictor design. Our experimental results on eight SPEC2000 benchmark programs reveal that a SPA predictor with 4-way set-associative PHT using 7-tag bit yields the highest prediction accuracy.
Keywords
benchmark testing; instruction sets; parallel architectures; program compilers; table lookup; PHT; aliasing; branch outcomes; branch prediction; interference rate; internal conflict; pattern aliasing; pattern history table; scalable per-address branch predictor; value locality; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
TENCON 2004. 2004 IEEE Region 10 Conference
Print_ISBN
0-7803-8560-8
Type
conf
DOI
10.1109/TENCON.2004.1414555
Filename
1414555
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