Accelerating SVD on reconfigurable hardware for image denoising

This paper presents the implementation on FPGA of a block SVD method for image denoising. This method exploits the fact that only the smallest singular values are affected by the noise and therefore can be discarded, leading to an efficient nonlinear image filtering. An efficient architecture for singular value decomposition, (SVD) based on the Brent, Luk, Van loan (BLV) systolic array, has been proposed. The architecture is three times more efficient and three times faster than the existing BLV structure. An optimised implementation has been efficiently carried out on the PP-RC1000 board using a high level language "Handel-C" for hardware design.