Improved design and characterisation method for ECL very high speed circuits

A procedure to design and characterise high speed bipolar circuits is presented. The design method is improved by using iso base-collector capacitance curves and duty cycles plots in the (IC, Vce) plane. This new optimisation way gives the optimum electrical parameters for each transistor of a bipolar circuit to reach the best trade-off between the switching speed and the power consumption. Furthermore, input signals time jitter is taken into account during simulations. The measurement method is improved by characterising in time domain each part of the measurement set-up. These improvements have enabled the design and characterisation of InP-DHBT D-type flip-flop and demultiplexer circuits. 40 Gbit/s on wafer measurement are presented.