Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems

This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.