Author_Institution :
Dept. of Comput. Sci. & Eng., East China Univ. of Sci. & Technol., Shanghai, China
Abstract :
The formal modelling and verification method has become an effective way of improving the reliability and correctness of complex, safety-critical embedded systems. Statecharts are widely used to formally model embedded applications, but they do not realise the reasonable separation of system concerns, which would result in code scattering and tangling. Aspect-Oriented Software Development (AOSD) technology could separate crosscutting concerns from core concerns and identify potential problems in the early phase of the software development life cycle. Therefore, the paper proposes aspect-oriented timed statecharts (extended timed statecharts with AOSD) to separately model base functional requirements and other requirements (e.g., scheduling, error handling), thereby improving the modularity and development efficiency of embedded systems. Furthermore, the dynamic behaviours of embedded systems are simulated and analysed to determine whether the model satisfies certain properties (e.g., liveness, safety) described by computation tree logic formulae. Finally, a given case demonstrates some desired properties processed with respect to the aspect-oriented timed statecharts model.
Keywords :
aspect-oriented programming; embedded systems; formal verification; safety-critical software; aspect-oriented design method; aspect-oriented software development technology; aspect-oriented timed statechart model; base functional requirements; code scattering; complex safety-critical embedded system correctness; complex safety-critical embedded system reliability; computation tree logic formulae; development efficiency; embedded system dynamic behaviour; error handling; formal modelling-verification method; modularity efficiency; software development life cycle; Automata; Computational modeling; Embedded systems; Error analysis; Object oriented modeling; Processor scheduling; Service-oriented architecture; Software reliability; Unified modeling language; computation tree logic; embedded systems; model checking; timed statecharts;