Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits

Power models are at the heart of high-level estimation methods used for industrial power evaluation of FPGA-based electronic designs. In this paper, probabilistic power estimation models of binary divider IP cores implemented in reconfigurable logic are presented. The models are ready for use at the algorithmic and RTL levels of the design flow and are simulation-independent, thus resulting in fast estimation times. The only parameters the model needs are the bit-widths of the operator inputs and their signal statistics: mean values, variances and autocorrelation coefficients. Based on these parameters and taking into account the particular logic structure of the binary divider cores, analytical probabilistic formulas are used to calculate the overall switching activity in the circuits-the main cause of dynamic power consumption. Estimates are compared with both real on-board measurements and estimates from the simulation-based tool XPower from Xilinx. Results show that the mean relative estimation errors are within 10% of on-board measurements or low-level estimates, and the average time to obtain power estimates using the proposed models is only 135 ms.