Effects of drain to gate stress on NMOSFET with polysilicon/Hf-silicate gate stack

Negative bias stress on the gate of an nMOSFET causes more damage than positive bias stress in terms of interface states density and accordingly, subthreshold swing degradation. A similar situation to negative bias stress on the gate occurs at the edge of the drain when the gate is off and the drain bias is on. This drain to gate stress causes asymmetric degradation of the channel and subthreshold swing increase. It is more prominent in MOSFETs with small gate length. It is believed to be due to the high geometric ratio of the stressed region to channel. Therefore, it must become a serious challenge to further device scaling.