An innovative multi-via test structure for wafer-level isothermal electromigration

An innovative multi-via test structure is developed for the isothermal electromigration (Iso-EM) test, which is a well-known wafer-level reliability (WLR) test methodology. The proposed test structure consists of a metal line with more than one via at both ends. The multi-via can reduce the current density in the vias and prevent the vias from abnormal damage by the high stress induced local joule heating during the Iso-EM test. By suitably selecting the number of vias, we make this stress current density on metal stripes and vias more uniform. The Iso-EM results correlated very well with those of the package-level EM tests on aluminum (Al) as well as copper (Cu) processes.