Improvement of spacer particle induced reliability failures

The poly pillar is a type of defect found in 0.18 μm logic based processes, which induces severe yield impact and high temperature operating life (HTOL) test failures. The root cause is the poor quality of SiON growth on the gate-poly layer. The non-uniform grain size makes the etching rate different, and thus induces poly pillars formed after poly etch. In addition, after spacer oxide deposition and the subsequent spacer etch, spacer particles are observed since the spacer film enlarges the poly pillar. Serious spacer particles cause not only chip probe (CP) yield loss but also reliability failures, like burn-in and gate oxide integrity tests failures. To solve this problem, we use a two-step poly etch recipe to replace the one-step poly etch recipe so as to differentiate etching selectivity between SiON and gate-poly effectively. In order to achieve more stringent reliability targets when technology enters into the deep sub-micron era, we apply a wafer-level reliability control system to facilitate reliability monitoring in a timely manner.