DocumentCode :
433517
Title :
Yield enhancement techniques in analog design automation
Author :
Hagglund, R. ; Hjalmarson, E. ; Wanhammar, L.
Author_Institution :
Dept. of Electrical Engineering, Linkoping University, SE-581 83 Linkoping, Sweden
fYear :
2004
fDate :
8-9 Nov. 2004
Firstpage :
305
Lastpage :
308
Abstract :
In this paper, two techniques that allow simultaneous sizing and yield enhancement of analog circuit are evaluated. Both methods use first-order sensitivity information to predict the performance degradation due to process variations. The methods are incorporated in an analog design automation tool that is used to design a large number of circuits in order to evaluate the approaches. Experimental results show that the two methods can be used to produce circuits with high yield while keeping the computational effort low.
Keywords :
Analog circuits; Degradation; Design automation; Electronic mail; Integrated circuit manufacture; Integrated circuit yield; Manufacturing processes; Measurement; Robustness; Yield estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Norchip Conference, 2004. Proceedings
Conference_Location :
Oslo, Norway
Print_ISBN :
0-7803-8510-1
Type :
conf
DOI :
10.1109/NORCHP.2004.1423884
Filename :
1423884
Link To Document :
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