Yield enhancement techniques in analog design automation

In this paper, two techniques that allow simultaneous sizing and yield enhancement of analog circuit are evaluated. Both methods use first-order sensitivity information to predict the performance degradation due to process variations. The methods are incorporated in an analog design automation tool that is used to design a large number of circuits in order to evaluate the approaches. Experimental results show that the two methods can be used to produce circuits with high yield while keeping the computational effort low.