A parallel scheme for implementing multialphabet arithmetic coding in high-speed programmable hardware

In this paper, a scheme is proposed for parallel-pipelined implementation of the multialphabet arithmetic-coding algorithm used in lossless data compression. Using this scheme, it is possible to parallelize both the encoding and decoding operations used respectively in data compression and decompression. The compression performance of the proposed implementation for both order 0 and order 1 models have been evaluated and compared with existing sequential implementations in terms of compression ratios as well as the execution time using the Canterbury corpus benchmark set of files. The proposed scheme also facilitates hardware realisation of the respective modules and hence is suitable for integration into embedded microprocessor systems, an important area where lossless data compression is applied.