ASIC hardware focused comparison for hash functions MD5, RIPEMD-160, and SHS

Author

Satoh, Akashi ; Inoue, Tadanobu

Author_Institution

IBM Res., Tokyo, Japan

Volume

1

fYear

2005

fDate

4-6 April 2005

Firstpage

532

Abstract

The hash functions MD5, RIPEMD-160, and SHA-1/224/256/384/512 were implemented by using a 0.13μm CMOS standard cell library with two synthesis options, area and speed optimizations, and their performances were evaluated. The smallest circuit of 8.0 Kgates with a throughput of 929 Mbps, and the highest throughput of 2.9 Gbps with 27.3 Kgates were obtained for SHA-1 and SHA-384/512 respectively. In terms of overall performance with consideration of the security levels, we conclude that SHA-256 is the best algorithm, with compact circuits of 11.5 ∼ 15.3 Kgates and high throughputs of 1.1 ∼ 2.4 Gbps. Our implementations also showed the highest throughputs for all of the hash functions in comparison with the state of the art.

Keywords

CMOS integrated circuits; application specific integrated circuits; cryptography; microprocessor chips; performance evaluation; 0.13 micron; 2.9 Gbit/s; 929 Mbit/s; ASIC hardware; CMOS standard cell library; MD5; RIPEMD-160; SHA-1; SHA-224; SHA-256; SHA-384; SHA-512; SHS; hash functions; performance evaluation; security levels; speed optimization; Authentication; Circuit synthesis; Cryptography; Data security; Digital signatures; Laboratories; Libraries; NIST; Performance evaluation; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology: Coding and Computing, 2005. ITCC 2005. International Conference on

Print_ISBN

0-7695-2315-3

Type

conf

DOI

10.1109/ITCC.2005.92

Filename

1428517