On the masking countermeasure and higher-order power analysis attacks

Masking is a general method used to thwart differential power analysis, in which all the intermediate data inside an implementation are XORed with random Boolean values. As a consequence, the power consumption of the running implementation becomes unpredictable, making first-order power analysis attacks unpractical. Several recent works have shown that such protected designs are still susceptible to higher-order power analysis attacks. In this paper, we propose an extension of the previously introduced higher-order techniques, based on a more general power consumption model, and evaluate its actual feasibility. In particular, we discuss the number of power traces required to mount successful attacks. We also illustrate how this number is affected by parallel computations, making certain implementation contexts (e.g. smart cards, 8-bit processors) more susceptible than others (e.g. FPGAs, ASICs).