Reconfigurable hardware for addition chains based modular exponentiation

In several public-key cryptosystems, the main operation consists of the modular exponentiation, which is performed using successive modular multiplications. The size of the operands that are used in these cryptosystems is considerably large (1024 bits), consuming a considerable amount of time. This impacts on the performance of the cryptosystem, especially in real time applications. In order to reduce the execution time in these cryptosystems, the total number of modular multiplications must be reduced. There are several methods that attempt to reduce this number either by partitioning the exponent in windows or by reducing the number of elements to be multiplied. In this paper, we propose a fast and compact reconfigurable hardware for computing modular exponentiation using the addition-chain methods.