Title :
An hardware efficient deblocking filter for H.264/AVC
Author :
Cheng, Chao-Chung ; Chang, Tian-Sheuan
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
This work presents an efficient VLSI architecture for the deblocking filter in H.264/AVC standard. The computing flow is reordered for easy hardware implementation. The resulting design can achieve 100 MHz with a gate count of 9.16 K when synthesized from Verilog RTL design by using UMC 0.18 μm CMOS technology. When clocked at 82.58 MHz, our design can easily support real-time deblocking of 2K × 1K @ 30 Hz video application; this high performance can meet high resolution real-time application requirement.
Keywords :
CMOS integrated circuits; VLSI; adaptive filters; code standards; hardware description languages; image resolution; real-time systems; video coding; 0.18 micron; 100 MHz; 82.58 MHz; H.264/AVC standard; UMC CMOS technology; VLSI architecture; Verilog RTL design; hardware efficient deblocking filter; high resolution video; real-time deblocking; Adaptive filters; Automatic voltage control; Buffer storage; Chaos; Computer architecture; Discrete cosine transforms; Filtering; Hardware; Shift registers; Very large scale integration;
Conference_Titel :
Consumer Electronics, 2005. ICCE. 2005 Digest of Technical Papers. International Conference on
Print_ISBN :
0-7803-8838-0
DOI :
10.1109/ICCE.2005.1429804
