Hardware implementation of a fault recovery protocol compliant with interbus-S standard

In this paper the authors present an hardware implementation of interbus-S protocol sub-blocks which include an extension of the protocol that manage the fault recovery capability. The fault recovery protocol is based on the definition of a novel device called master/slave able to recover any occurring fault. The master/slave device will be implemented into an FPGA chip. It contains the physical layer and a portion of data link and they are described through VHDL language. Gate level simulations are carried out to verify the functionality and compatibility with interbus-S of the fault recovery protocol.