• DocumentCode
    435518
  • Title

    Substrate-well modeling for DSM triple-well CMOS digital circuits with adjustable VT

  • Author

    Ionita, Razvan ; Vladimirescu, Andrei

  • Author_Institution
    Inst. Superieur d´´Electron. de Paris, France
  • fYear
    2004
  • fDate
    6-8 Dec. 2004
  • Firstpage
    274
  • Lastpage
    277
  • Abstract
    A distributed model of the substrate well is developed in order to characterize the performance of CMOS standard-cell circuits with adjustable VT implemented in a triple-well process. This model is used to study the impact of the number of gates placed in the same well on performance and to draw conclusions for optimal design. A lumped equivalent network of the well is derived as a function of the number of gates in the well. The impact of the well contact placement and the resistance between the well contacts and the bulk of the transistors is analyzed for standard-cells on logic circuits.
  • Keywords
    CMOS digital integrated circuits; equivalent circuits; integrated circuit design; integrated circuit modelling; logic circuits; logic design; logic gates; lumped parameter networks; CMOS digital circuits; CMOS standard cell circuits; deep submicron triple well process; distributed model; logic circuits; logic design; logic gates; lumped equivalent network; substrate well modeling; transistors; CMOS digital integrated circuits; CMOS process; Digital circuits; Electronic mail; Isolation technology; MOS devices; Routing; SPICE; Semiconductor device modeling; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on
  • Print_ISBN
    0-7803-8656-6
  • Type

    conf

  • DOI
    10.1109/ICM.2004.1434265
  • Filename
    1434265
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=435518