Title :
Taking silicon to the limit: challenges and opportunities
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Silicon-based CMOS transistors can be scaled well into the sub-10nm regime. However, new materials and processes, in conjunction with advanced transistor structures, are needed for nanometer-scale MOSFETs to meet ITRS performance specifications. This paper discusses challenges for achieving target performance metrics at the end of the roadmap, and approaches to overcoming them.
Keywords :
CMOS integrated circuits; MOSFET; nanoelectronics; ITRS; nanometer-scale MOSFET; performance metrics; performance specifications; silicon-based CMOS transistors; transistor structures; CMOS technology; Costs; Doping; FETs; FinFETs; Leakage current; MOSFETs; Semiconductor materials; Silicon; Transistors;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1434943
