Optimized deep-submicron MOS transistor for low power application

As MOSFET device scales toward deep-submicron, subthreshold gate and band-to-band tunneling leakage current become a significant part of power consumption. Low power MOSFET device can be developed from generic fabrication process and device architecture. Once gate length and gate oxide thickness are selected, the most important process changes are implant conditions that include channel, halo and source/drain extension (SDE) implant. Implementation of dual SDE and halo implant has been confirmed to be the key process change, which not only reduces the off-state leakage current of a MOS device, but also improves drive current of low power MOS device significantly.