Three-dimensional stacked-Fin-CMOS integrated circuit using double layer SOI material

In this work, a stacked 3D Fin-CMOS (SF-CMOS) technology is developed to double the device packing density of conventional FinFET. The key features of this architecture include: (1) high scalability inherent from the FinFET structure; (2) high density with more than 50% area reduction compared to the conventional 2D architecture; (3) reduced interconnect wiring distance between the n-channel and the p-channel devices; and (4) compatibility with conventional 2D CMOS technology. To implement the 3D SF-CMOS, we utilized a double layer SOI wafer with two single crystalline silicon layers isolated by an oxide layer. 3D SF-CMOS inverters were demonstrated with the n-channel FinFET stacking on the top of the p-channel FinFET.