DocumentCode :
435703
Title :
Unique capacitance phenomenon of a 100nm double-gate FD SOI NMOS device with n+/p+ poly top/bottom gate
Author :
Yang, C.P. ; Hsu, C.H. ; Kuo, J.B.
Author_Institution :
Dept of Electr. Eng., National Taiwan Univ., Taipei, Taiwan
Volume :
1
fYear :
2004
fDate :
18-21 Oct. 2004
Firstpage :
106
Abstract :
This paper reports the unique capacitance phenomenon of 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n+/p+ poly top/bottom gate. Based on the 2D simulation result, the gate-drain/source capacitance (CGD/CGS) of the device shows a sudden fall at the gate voltage of 0.5V due to the existence of the hole accumulation/depletion in the bottom channel controlled by the p+ bottom gate.
Keywords :
MOS integrated circuits; capacitance; silicon-on-insulator; 100 nm; 2D simulation; capacitance phenomenon; double-gate FD SOI NMOS device; gate-drain/source capacitance; hole accumulation/depletion; poly top/bottom gate; Capacitance; Capacitance-voltage characteristics; Doping; MOS devices; Transistors; Very large scale integration; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
Type :
conf
DOI :
10.1109/ICSICT.2004.1434964
Filename :
1434964
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=435703
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