DocumentCode :
435740
Title :
Fully-depleted SOI devices with elevated source/drain structure
Author :
Lian, Jun ; Hai, Chaohe
Author_Institution :
Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China
Volume :
1
fYear :
2004
fDate :
18-21 Oct. 2004
Firstpage :
287
Abstract :
0.35μm thin-film fully-depleted SOI CMOS devices with elevated source/drain structure were fabricated by novel technology. Key process technologies were demonstrated. The devices have quasi-ideal subthreshold properties; the subthreshold slope of NMOSFETs and is 65mv/decade, while the subthreshold slope of PMOSFETs is 69mv/decade. The saturation current of NMOSFETs and PMOSFETs is 375μA/um and 170μA/um either. The saturation current of 1.2μ NMOSFETs was increased by 32% with elevated source/drain structure. The saturation current of 1.2μm PMOSFETs was increased by 24%. The per-stage propagation delay of 101-stage SOI CMOS ring oscillator is 75ps with 3 V supply voltage.
Keywords :
CMOS integrated circuits; MOSFET; silicon-on-insulator; 0.35 micron; 3 V; NMOSFET; PMOSFET; SOI CMOS devices; SOI CMOS ring oscillator; elevated source/drain structure; thin film; Amorphous silicon; Etching; Implants; MOSFETs; Silicides; Space technology; Temperature; Thin film devices; Tiles; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
Type :
conf
DOI :
10.1109/ICSICT.2004.1435008
Filename :
1435008
Link To Document :
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