Design guidelines of nano-scaled SOI-DTMOS device

The paper suggests nano-scaled SOI-DTMOS and expects to obtain high performances with standard technology, and relax the critical requirement of silicon film thickness for conventional SOI to provide greater design choices of nano-scaled devices. The paper compares scaling-down capabilities of the devices at nanometer and points out the advantages of SOI-DTMOS. In details, the paper discusses the critical structure parameter - silicon film thickness. From research we find that at nano-scaled gate lengths the novel device SOI-DTMOS with excellent performances of both high speed and low power, is able to relax the critical requirement of silicon film thickness that strictly limits the application of conventional body-floating SOI. Finally, the paper provides general guidelines for tsi choosing on the basis of analyzing SOI-DTMOS device physics, and obtains proper parameter values for the practical manufacturing.