Junction formation in advanced planar and vertical devices

Fundamental changes are imminent for high-performance Si CMOS, for materials as well as for the device architecture. The impact of these changes on junction formation will be reviewed in this paper. It is no longer possible to use "junction depth" as a metric for short-channel effects since the junction in reality is two-dimensional. The lateral junction, or overlap, becomes dominant for deeply scaled bulk devices or replaces junction depth for ultra-thin body devices, where the vertical junction is limited by a geometric constraint. The optimum overlap is quite small, or may even be negative, making a process without the need of high-tilt implantation feasible, even for dopant activation with negligible diffusion by flash annealing or laser thermal processing. Dopant activation by solid phase epitaxial regrowth might require high-tilt implants for a positive overlap. The use of such implants, however, is expected to lead to severe gate-poly and potentially fatal gate oxide degradation. Advanced devices have to be designed ever closer to the "edge" and consequently small changes in processing parameters are beginning to have a disproportionate impact on device characteristics.