A novel reverse read array architecture for embedded SONOS type flash memory

Author

Dong, Wu ; Liyang, Pan ; Lei, Sun ; Zhaojian, Zhang ; Zhigang, Duan ; Guangjun, Yang ; Jun, Zhu

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

Volume

1

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

699

Abstract

The reverse read characteristics of SONOS type flash memory is researched and a novel array architecture with reverse read operation is proposed in this paper. A divided common-source-line NOR architecture is adopted to realize reverse read operation which enlarges the difference of the threshold voltage between the erased cell and the programmed cell and accelerates the read operation. Meanwhile, it also reduces the program disturbance, simplifies the source-line decoder, high voltage switch circuit and charge pump design.

Keywords

flash memories; memory architecture; semiconductor-insulator-semiconductor structures; NOR architecture; array architecture; charge pump design; common-source-line architecture; embedded SONOS flash memory; high voltage switch circuit; program disturbance; reverse read operation; source-line decoder; Channel hot electron injection; Circuit synthesis; Electron traps; Flash memory; Microelectronics; Nonvolatile memory; SONOS devices; Sun; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1435099

Filename

1435099