DocumentCode :
435814
Title :
Meeting Si challenges: nano technology development in China
Author :
Chen, John ; Gao, David ; Zhu, Bei ; Mo, Hongxiang ; Wu, Hanming ; Ning, Jay ; Chen, Steven ; Sun, Peter ; Yang, Simon
Author_Institution :
Semicond. Manuf. Int. Corp., Beijing, China
Volume :
1
fYear :
2004
fDate :
18-21 Oct. 2004
Firstpage :
714
Abstract :
Leading edge technologies are essential lo the foundry success in mainland China. In this paper, 90 nm and beyond technology with 1.2 nm physical gate oxide, strained silicon, NiSi and low-k Cu interconnection for high performance logic is presented. A highly manufacturable technique for improving transistor performance is reported.
Keywords :
elemental semiconductors; integrated circuit interconnections; nanotechnology; semiconductor technology; silicon; 1.2 nm; 90 nm; China; NiSi interconnection; Si; gate oxide; high performance logic; low-k Cu interconnection; nanotechnology development; strained silicon; Annealing; Dielectric devices; Leakage current; MOS devices; MOSFETs; Manufacturing; Plasma density; Plasma devices; Silicon; Sun;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
Type :
conf
DOI :
10.1109/ICSICT.2004.1435103
Filename :
1435103
Link To Document :
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