Title :
A triple gate oxide logic process for 90nm manufacturing technology
Author_Institution :
United Microelectron. Corp., Hsinchu, Taiwan
Abstract :
We have developed 90 nm-node CMOS technology for general-purpose system-on-a-chip (SoC), in which both high performance and low leakage devices are strongly required. With highly reliable triple gate oxide (1.55nm, 2.2nm and 5.2nm) and multi-Vt options, this platform offers broad foundry applications. The standard performance (SF) transistors provide on-current of 910/405 μA/μm for n/pFETs with off-current of 8/16 nA/μm respectively. The low leakage (LL) transistors provide on-current of 450/170 μA/μm for n/pFET´s with off-current of 30/30 pA/μm. These transistors are incorporated with optimized triple well, nitrided gate oxide dielectrics, ultra shallow junction, offset oxide spacer, low temperature nitride spacer and low temperature cobalt salicide to optimize the device performance. A 9-level hierarchical Cu/low-k BEOL integration is implemented to maximize interconnects speed. Two embedded SRAM cells are provided for high performance and low leakage options.
Keywords :
CMOS logic circuits; SRAM chips; logic design; nanotechnology; system-on-chip; 1.55 nm; 2.2 nm; 5.2 nm; 90 nm; CMOS technology; Cu/Low-k BEOL integration; embedded SRAM cells; general-purpose system-on-a-chip; low leakage devices; low leakage transistors; low temperature cobalt salicide; low temperature nitride spacer; nitrided gate oxide dielectrics; offset oxide spacer; optimized triple well; triple gate oxide logic process; ultra shallow junction; CMOS logic circuits; CMOS technology; Cobalt; Dielectric devices; Foundries; Logic devices; Logic gates; Manufacturing processes; System-on-a-chip; Temperature;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1435104
