Novel VLSI architecture of 2-D DWT/IDWT for JPEG2000 based on diagonal storage

Author

Qin, Xing ; Yan, Xiao-Lang ; Yang, Chong-Pong ; Zhao, Xing

Author_Institution

Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China

Volume

3

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1657

Abstract

An efficient VLSI architecture of 2D DWT/IDWT for JPEG2000 is proposed. In this architecture, the memory consists of eight dual port SRAM memories where image data is diagonally stored, and a 1D DWT based lifting scheme is implemented using pipeline processing techniques. The 1D DWT core can process 4 sample data in a clock cycle. According to different requirement, this architecture can be implemented with or without an external buffer. Simulation results show that this design is able to perform a 3-level decomposition for a 512×512 grayscale image within 13.3 ms (with an external buffer), or 16.6 ms (without an external buffer) when running at 20 MHz.

Keywords

SRAM chips; VLSI; discrete wavelet transforms; image coding; pipeline processing; 13.3 ms; 16.6 ms; 1D DWT based lifting scheme; 20 MHz; 262144 pixel; 2D DWT; 2D IDWT; 512 pixel; JPEG2000; SRAM; VLSI architecture; diagonal storage; diagonally stored image data; dual port memories; external buffer; grayscale image; pipeline processing; three-level decomposition; Clocks; Discrete wavelet transforms; Filters; Memory architecture; Memory management; Pipeline processing; Random access memory; Throughput; Tiles; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1435149

Filename

1435149