Unified model for on-chip interconnects

In this paper, we present a compact unified model for on-chip interconnects, which includes a quasi-3D capacitance model and an effective loop inductance model. To effectively model three-dimensional fringe components in the capacitance model, we propose a novel concept of effective width for a 3D wire, which provides a physics-based approach to decompose any 3D structure into a series of 2D segments. To construct analytic and hierarchical model of loop inductance, an effective loop inductance approach is studied. In particular, we show empirically that high-frequency signal propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance. The capacitance and inductance models are combined into a unified frequency-dependent RLC model describing successfully the wide-band characteristics of on-chip interconnects up to 100GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model. Regarding coupled wire, the impact of resistance matrix on crosstalk noise is studied. The off-diagonal terms of resistance matrix are related to return path, which is important for accurate noise modeling at high frequency. It is shown that the error in crosstalk peak noise can be significant if the return path resistance is ignored.