Efficient 3-D interconnect capacitance extraction based on direct solving techniques for system with multiple right-hand sides

Under the current deep submicron technology, the capacitance extraction of interconnects has become more and more important and more coupling capacitances need to be extracted accurately rather than those related with a single master net for high-precision time verification. Therefore, for a simulated structure, IV voltage must be set on different conductors one by one and the corresponding linear system with multiple right-hand sides (RHS) should be solved efficiently. In this paper, direct equation solving techniques are presented to extract the parasitic capacitances with multiple master conductors. Combined with the quasi-multiple medium (QMM) technology, our method exploits the sparsity of the resulted coefficient matrix and is very suitable for the problem with multiple RHS. The experiments on actual interconnect structures have shown that our method is several times faster than the conventional GMRES solver, while preserving the computational accuracy.