3D-IC performance computing of single-gate SOI CMOS inverter

Based on Elmore delay model and 3D-IC interconnection model and 2003 ITRS, we compute two parameters of interconnection time delay (T_N) and power delay product (PDP) in which facing 3D-IC (N gates and m device layers) of single-gate SOI CMOS inverter and running VC++ and Excel. T_N and PDP are constructed in case of a 3D-IC net with both horizontal and vertical wire. A major focus on analyzing T_N and PDP is given by finding their non-line factors β₁, β₂ and β₃ which result mainly from the vertical wire contribution. The parabola-shape β₁ of T_N can reveal that T_N has minimum when m = 6 - 8. The flat peak parabola-shape β₂ of PDP´s dynamic component (about netload C. V_dd and f_elk) can be observed when 2003 ITRS is in 90nm-22nm technology nodes. The semi-U-shape β₃ of PDP´s static component (about I_off and V_dd) can reveal that PDP has minimum when in 90nm-45nm technology nodes. To sum up, in 90nm-45nm technology nodes of 2003 ITRS, when device layers m = 6 - 8, then T_N and PDP of 3D-IC net have their minimum.