DocumentCode
435976
Title
Constraint-based watermarking technique for hard IP core protection in physical layout design level
Author
Ni, Min ; Gao, Zhiqiang
Author_Institution
Instn. of Microelectron. Eng., Tsinghua Univ., Beijing, China
Volume
2
fYear
2004
fDate
18-21 Oct. 2004
Firstpage
1360
Abstract
A new watermarking method for hard IP core copyright protection in physical layout design level based on the constraint concept is presented. It can apply to both VLSI design IP core and full-custom design IP core. The principle is proposed and the watermarking design flow using commercial EDA design tools is discussed. The experiment method to validation our approach is also included in this paper.
Keywords
VLSI; copyright; integrated circuit layout; watermarking; EDA design tools; VLSI design IP core; constraint-based watermarking; copyright protection; full-custom design IP core; hard IP core protection; physical layout design level; Constraint optimization; Copyright protection; Design engineering; Electronic design automation and methodology; Microelectronics; Pulp manufacturing; Routing; Timing; Very large scale integration; Watermarking;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN
0-7803-8511-X
Type
conf
DOI
10.1109/ICSICT.2004.1436805
Filename
1436805
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