Title :
A PCI target device with re-reusing PCI AD bus
Author :
Zhou, Gan-Min ; Gao, Ming-Lun ; Hu, Yong-Hua ; Cao, Hua-Feng
Author_Institution :
Inst. of VLSI Design, Hefei Technol. Univ., China
Abstract :
In this paper we bring forward a new technology to re-reuse the PCI AD bus based on the timing sharing reuse technology. It makes the peripheral device can use the PCI AD bus to receive and send data from and to the master device. Though need to design relatively complicated control logic, using the technology to design a chip can approximately reduce 52% of the chip´s area. Using 0.35μm CHARTERED CMOS technology, the area of the chip is 4.2×3.7mm2.
Keywords :
CMOS logic circuits; logic design; microprocessor chips; peripheral interfaces; system buses; 0.35 micron; 3.7 mm; 4.2 mm; CHARTERED CMOS technology; PCI AD bus; PCI target device; chip design; data receiving; data sending; master device; peripheral device; timing sharing reuse technology; CMOS logic circuits; CMOS technology; Chip scale packaging; Clocks; Costs; Logic design; Logic devices; Manufacturing; Timing; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1436820
