Power management for modern VLSI loads using dynamic voltage scaling

Modern deep sub-micron MOS devices suffer from a significant amount of DC leakage power dissipation due to the tunneling current across the ultra-thin gate oxide and off-state drain to source leakage, etc. In this paper, a dynamic voltage scaling (DVS) technique is demonstrated experimentally to provide an automated real-time control of the supply voltage according to the required VLSI core clock frequency. The DVS scheme is made practical with the use of a high efficiency sort-switching DC-DC converter and an on-chip frequency-to-voltage control loop. Using a 0.1 μm CMOS CPLD chip to serve as a typical VLSI load, a power saving of greater than 50% at 0.6 times the maximum clock frequency was observed. This DVS architecture is suitable for managing the power consumption of modern VLSI chips where the demand on processing rate varies constantly.