Title :
Zero-forcing block linear equalizer implementation based on ADSP-TS101 for TD-SCDMA
Author :
Peng, Cong ; Zhou, Chunhui ; Zhao, Ming ; Yao, Yan
Author_Institution :
Res. Inst. of Inf. Technol., Tsinghua Univ., Beijing, China
fDate :
31 Aug.-4 Sept. 2004
Abstract :
This paper introduces the hardware structure and performance of TigerSHARC® DSP, the zero-forcing block linear equalizer (ZF-BLE) for TD-SCDMA, and how to implement ZF-BLE based on TigerSHARC® DSP in the VisualDSP++3.0 software environment, considering the hardware structure of ADSP-TS101. The results indicates that ZF-BLE can be implemented with high efficiency based on ADSP-TS101 and just 4 chips of TS101 can supports joint-detection (JD) of 16 lower-bit-rate speech users for TD-SCDMA.
Keywords :
code division multiple access; digital signal processing chips; equalisers; multiuser detection; time division multiple access; ADSP-TS101; TD-SCDMA; TigerSHARC® DSP; VisualDSP++3.0 software environment; hardware structure; multiuser detection; zero-forcing block linear equalizer implementation; Digital signal processing; Digital signal processing chips; Equalizers; Hardware; Information technology; Multiple access interference; Multiuser detection; Software performance; Speech; Time division synchronous code division multiple access;
Conference_Titel :
Signal Processing, 2004. Proceedings. ICSP '04. 2004 7th International Conference on
Print_ISBN :
0-7803-8406-7
DOI :
10.1109/ICOSP.2004.1452624
