• DocumentCode
    437032
  • Title

    The new architecture for high performance signal processing system

  • Author

    He, Bin ; Wang, Xiaonan

  • Author_Institution
    Sch. of Information Sci., Beijing Chem. Technol. Univ., China
  • Volume
    1
  • fYear
    2004
  • fDate
    31 Aug.-4 Sept. 2004
  • Firstpage
    511
  • Abstract
    Based on the rapid IO protocol, the new architecture, winch is based on the peer-to-peer, for high performance multi-DSP (digital signal processor) signal processing system is introduced. The new architecture has advantages in expansibility, performance and cost, etc. The overall system is composed of many DSPs and many FPGAs (field programmable gate array). The FPGA is a network co-processor, which is used to connect multi-DSP. The FPGA implementation of the network co-processor is discussed in detail and the system performance is also given.
  • Keywords
    field programmable gate arrays; protocols; signal processing; digital signal processor; field programmable gate array; rapid IO protocol; signal processing system; Array signal processing; Coprocessors; Costs; Digital signal processing; Digital signal processors; Field programmable gate arrays; Peer to peer computing; Protocols; Signal processing; Winches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signal Processing, 2004. Proceedings. ICSP '04. 2004 7th International Conference on
  • Print_ISBN
    0-7803-8406-7
  • Type

    conf

  • DOI
    10.1109/ICOSP.2004.1452694
  • Filename
    1452694