Discrete wavelet transform IPcore design for image compression

Discrete wavelet transform (DWT), which is recently used by some international standard organizations in image compression protocols, has an excellent performance on multiresolution representation. Because of DWT´s computation-intensive nature, however, it seldom meets the application of real-time video system. Field programmable gate array (FPGA) has the advantages as parallel, high-speed, and easy-modification. These merits make FPGA the appropriate choice for the DWT implementations. This paper describes an IPcore design based on hardware description language (HDL), and implemented on an FPGA device. The core uses distributed arithmetic, parallel operation, and pipelining design. In addition, the IPcore technology protects and encapsulates the design of the image compression core.