A platform-based architecture of loop filter for AVS

AVS is Chinese new audio and video coding standard, in which a loop filter has been applied to remove blocking artifacts. A platform-based architecture for the loop filter of AVS standard is proposed in this paper. The advantages of column-separated SRAM organization and two configurable matrix transposers have been adopted to accelerate loop filtering in this architecture. The architecture has been described in Verilog HDL, simulated with VCS and synthesized using 0.18 μm CMOS cells library by Synopsys Design Compiler. The circuit totally costs about 38 k logic gates when the working frequency is set to 150 MHz. Simulation results show that the architecture can support real-time loop filter of HDTV (1280×720, 60 fps) AVS video. This architecture is valuable for the hardware design of AVS codec.