Parametric data-parallel architectures for TLM acceleration

Author

Chouliaras, Vassilios A. ; Flint, James A. ; Li, Yibin

Author_Institution

Dept. of Electron. & Electr. Eng., Loughborough Univ., UK

fYear

2004

fDate

1-4 Nov. 2004

Firstpage

569

Lastpage

572

Abstract

We discuss the architecture and microarchitecture of a scalable, parametric vector accelerator for the TLM algorithm. Architecture-level experimentation demonstrates an order of magnitude complexity reduction for vector lengths of 16 32-bit single-precision elements. We envisage the proposed architecture replicated in a SoC environment, thus forming a multiprocessor system capable of tapping. parallelism at the thread level as well as the data level.

Keywords

computational complexity; multiprocessing systems; parallel architectures; system-on-chip; transmission line matrix methods; vectors; 32 bit; SoC environment; TLM acceleration; TLM algorithm; complexity reduction; data level parallelism; microarchitecture; multiprocessor system; parametric data-parallel architectures; scalable parametric vector accelerator; single-precision elements; thread level parallelism; vector lengths; Acceleration; Communication system control; Computer architecture; Coprocessors; Instruction sets; Microarchitecture; Parallel processing; Reduced instruction set computing; Registers; SDRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Electromagnetics and Its Applications, 2004. Proceedings. ICCEA 2004. 2004 3rd International Conference on

Print_ISBN

0-7803-8562-4

Type

conf

DOI

10.1109/ICCEA.2004.1459419

Filename

1459419