Design of half-rate linear phase detector using MOS current-mode logic gates for 10-Gb/s clock and data recovery circuit

Author

Shin, Jong-Kil ; Yoo, Tae-Whan ; Lee, Mao-Seop

Author_Institution

Sch. of Eng., Inf. & Commun. Univ., Daejeon

Volume

1

fYear

0

fDate

0-0 0

Firstpage

205

Lastpage

210

Abstract

A 10 Gb/s clock and data recovery (CDR) circuits which extract the clock signal from non-return-zero (NRZ) random data stream are very important to the 10-gigabit -per-second integrated receivers. The half-rate linear phase detector for 10-Gb/s clock and data recovery (CDR) circuit is designed to 0.18-um standard CMOS technology. This half-rate phase detector is composed of four latches and two exclusive OR (XOR) gates. The proposed circuits of phase detector provide a linear characteristic and it has a configuration of MOS current-mode logic (MCML) gates

Keywords

CMOS integrated circuits; integrated circuit design; optical logic; optical receivers; phase detectors; synchronisation; 10 Gbit/s; CMOS integrated circuit design; MOS current-mode logic gate; XOR gate; clock and data recovery circuit; clock signal; half-rate linear phase detector; nonreturn-zero random data stream; optical receiver; CMOS technology; Clocks; Data mining; Detectors; Integrated circuit technology; Logic circuits; Logic design; Logic gates; Optical signal processing; Phase detection;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Technology, 2005, ICACT 2005. The 7th International Conference on

Conference_Location

Phoenix Park

Type

conf

DOI

10.1109/ICACT.2005.245826

Filename

1461769