DRAGO chip: a low-noise CMOS preamplifier-shaper for silicon drift detectors with on-chip JFET

We propose a CMOS preamplifier-shaper circuit designed to be used with silicon drift detectors (SDDs) for X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by a low-noise preamplifier and by a 6th order semiGaussian shaping amplifier with four selectable peaking times from 1.7 μs up to 6 μs. The integrated time constant used for the shaping is implemented by means of a recently proposed ´RC´ cell. This cell is based on the well known technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The particular solution here adopted allows a precise and stable implementation of the desired time constant, for given values of R and C, and guarantees low-noise performances of the shaping amplifier when used with a cooled SDD or other solid-state detectors with low leakage current. In this work, the main features of the circuit are first presented. The experimental results obtained in the characterization of the first prototype realized in the 0.35 μm AMS technology are then reported and discussed. The energy resolution measured using the chip with a SDD is 150 eV at 6 keV which corresponds to an electronics noise of 10.8 e^- rms.