Author :
Foudas, C. ; Bainbridge, R. ; Ballard, D. ; Church, I. ; Corrin, E. ; Coughlan, J.A. ; Day, C.P. ; Freeman, E.J. ; Fulcher, J. ; Gannon, W.J.F. ; Hall, G. ; Halsall, R.N.J. ; Iles, G. ; Leaver, J. ; Noy, M. ; Pearson, M. ; Raymond, M. ; Reid, I. ; Rogers,
Abstract :
The front end driver is a 9U 400mm VME64x card designed for reading out the CMS silicon tracker signals transmitted by the APV25 analogue pipeline ASICs. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GBytes/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS DAQ system using the S-LINK64 protocol at a maximum rate of 400 Mbytes/sec. All data processing algorithms on the FED are executed in large on-board FPGAs. Results on the design, performance, testing and quality control of the FED are presented and discussed.
Keywords :
application specific integrated circuits; data acquisition; field programmable gate arrays; nuclear electronics; position sensitive particle detectors; readout electronics; satellite computers; silicon radiation detectors; 9U 400mm VME64x card; APV25 analogue pipeline ASIC; CMS DAQ system; CMS silicon tracker signals; CMS tracker readout front end driver; FPGA; S-LINK64 protocol; data processing algorithms; noise subtraction; optical fibers; Clustering algorithms; Collision mitigation; Data acquisition; Optical fibers; Optical noise; Pipelines; Protocols; Signal design; Signal processing; Silicon;
