DocumentCode :
438321
Title :
Low-density parity-check codes with variable rate and randomized constraints for advanced magnetic tape recording
Author :
Li, Zongwang ; Xie, Jin ; Kumar, B. V K Vijaya
Author_Institution :
Data Storage Syst. Center, Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
2005
fDate :
4-8 April 2005
Firstpage :
1611
Lastpage :
1612
Abstract :
Variable rate and randomized run length limited (VR2 RLL) constraint is used in some magnetic tape recording systems. The variable rate encoding algorithm monitors the incoming data stream for conditions such as run length limit (RLL) constraints. If one of the conditions is violated, a bit is inserted into the data stream. The purpose of the VR2 RLL constraint is to ensure that the encoded data contains adequate tracking and amplitude information for reliable data detection and prevent the preamble pattern from occurring during the data field. Although the VR2 approach to RLL constraint is effective, it has the disadvantages of variable block length and error propagation. Furthermore, VR2 is not suitable for soft decision decoding needed by low-density parity check (LDPC) codes being investigated because of their good performance, low complexity and inherent parallel decoding architecture. LDPC codes usually exhibit excellent error correction performance and the LDPC decoder may be able to recover the codeword even if we deliberately introduce some errors in the codeword in order to satisfy RLL constraints. Based on this observation, the paper proposes a scheme of combining LDPC codes with the VR2 RLL constraint based on bit flipping. In addition to providing soft decision decoding to achieve large coding gain, the proposed scheme has the advantages of no error propagation and fixed block length.
Keywords :
error correction; magnetic recording; parity check codes; runlength codes; tape recorders; variable rate codes; advanced magnetic tape recording; bit flipping; data detection; data stream; error correction performance; error propagation; fixed block length; inherent parallel decoding architecture; large coding gain; low-density parity-check codes; randomized run length limited constraint; soft decision decoding; variable block length; variable rate encoding algorithm; Bit error rate; Decision support systems; Detectors; Encoding; Error correction codes; Iterative decoding; Linear feedback shift registers; Magnetic recording; Parity check codes; Virtual reality;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Magnetics Conference, 2005. INTERMAG Asia 2005. Digests of the IEEE International
Print_ISBN :
0-7803-9009-1
Type :
conf
DOI :
10.1109/INTMAG.2005.1464239
Filename :
1464239
Link To Document :
بازگشت