MAIA - a framework for networks on chip generation and verification

Author

Ost, Luciano ; Mello, A. ; Palma, José ; Moraes, Fernando ; Calazans, Ney

Author_Institution

FACIN-PUCRS, Porto Alegre, Brazil

Volume

1

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

49

Abstract

The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be developed to integrate NoC interconnection architectures and IP cores into SoCs. Such tools have to fulfill three main requirements: (i) automated NoC generation; (ii) automated production of NoC-IP core interfaces; and (iii) seamless analysis of NoC traffic parameters. The objective of this paper is to present the MAIA framework, which includes functions to address all these requirements. NoCs generated by the MAIA framework have been used to successfully prototype SoCs in FPGAs.

Keywords

integrated circuit design; integrated circuit interconnections; system-on-chip; FPGA; IP cores; MAIA framework; NoC interconnection architectures; NoC traffic parameters; NoC-IP core interfaces; SoC complexity; automated NoC generation; automated NoC-IP production; networks on chip; seamless traffic analysis; wires interconnection; Clocks; Field programmable gate arrays; Frequency estimation; Network-on-a-chip; Packet switching; Production; Prototypes; Telecommunication traffic; Traffic control; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466128

Filename

1466128