DocumentCode
438400
Title
Evaluation of on-chip transmission line interconnect using wire length distribution
Author
Inoue, Junpei ; Ito, Hiroyuki ; Gomi, Shinichiro ; Kyogoku, Takanori ; Uezono, Takumi ; Okada, Kenichi ; Masu, Kazuya
Author_Institution
Precision & Intelligence Lab., Tokyo Technol. Inst., Yokohama, Japan
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
133
Abstract
On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which are estimated with wire length distribution (WLD). Advantages of on-chip transmission line are discussed from the view point of delay time and power consumption.
Keywords
RC circuits; integrated circuit interconnections; RC interconnects; delay time reduction; on-chip transmission line interconnect; power consumption reduction; wire length distribution; Crosstalk; Delay effects; Distributed parameter circuits; Energy consumption; Integrated circuit interconnections; Power transmission lines; Repeaters; Transmission lines; Wire; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466145
Filename
1466145
Link To Document