Bridging fault detection in double fixed-polarity Reed-Muller (DFPRM) PLA

Author

Rahaman, Hafizur ; Das, Debesh K.

Author_Institution

Dept. of Inf. Technol., Bengal Eng. & Sci. Univ., Shibpur, India

Volume

1

fYear

2005

fDate

18-21 Jan. 2005

Firstpage

172

Abstract

Testable design for detecting stuck-at and bridging faults in programmable logic arrays (PLAs) based on double fixed-polarity Reed-Muller expression (DFPRM) is proposed. DFPRMs are generalized expressions of FPRM. It has advantages of compactness and easy testability. The EXOR part in the proposed design is implemented with tree structure that admits a universal test set. For an n-variable function, this design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR- and AND- type) and all single stuck-at faults. This tree based implementation reduces circuit delay significantly compared to cascaded EXOR-part.

Keywords

Reed-Muller codes; fault diagnosis; logic circuits; logic testing; programmable logic arrays; tree data structures; EXOR part; circuit-under-test; double fixed-polarity Reed-Muller; fault detection; programmable logic arrays; stuck-at faults; test vectors; tree structure; universal test set; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Genetic expression; Logic design; Logic testing; Programmable logic arrays; Tree data structures;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific

Print_ISBN

0-7803-8736-8

Type

conf

DOI

10.1109/ASPDAC.2005.1466152

Filename

1466152