DocumentCode
438412
Title
An efficient combinationality check technique for the synthesis of cyclic combinational circuits
Author
Agarwal, Vineet ; Kankani, Navneeth ; Rao, Ravishankar ; Bhardwaj, Sarvesh ; Wang, Janet
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Volume
1
fYear
2005
fDate
18-21 Jan. 2005
Firstpage
212
Abstract
It has been recently pointed out that cyclic circuits are not necessarily sequential, and cyclic topologies that are combinational generally have lower literal counts than their acyclic counterparts. However, the synthesis of cyclic combinational circuits is potentially expensive due to the need to explore a wide range of cyclic topologies and check each of them for combinationality. We first obtain the acyclic implementation of the given set of Boolean functions. Then using a branch-and-bound heuristic, we generate cyclic circuits that are to be checked for combinationality. Unlike earlier complex methods for combinationality check, our approach is to check whether this cyclic circuit is functionally equivalent to the acyclic circuit obtained earlier. While synthesizing cyclic circuits with the proposed method, we observed up to 45% improvements in the literal count (for Espresso and LGsynth93 benchmarks) over the acyclic circuit synthesized by the Berkeley sis package.
Keywords
Boolean functions; combinational circuits; logic testing; Boolean functions; branch-and-bound heuristic; circuit synthesis; combinationality check technique; cyclic combinational circuits; cyclic topology; Analytical models; Boolean functions; Circuit simulation; Circuit synthesis; Circuit topology; Combinational circuits; Data structures; Iterative algorithms; Sequential circuits; Sufficient conditions;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN
0-7803-8736-8
Type
conf
DOI
10.1109/ASPDAC.2005.1466160
Filename
1466160
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