Title :
Evaluation of the statistical delay quality model
Author :
Sato, Yasuo ; Hamada, Shuji ; Maeda, Toshiyuki ; Takatori, Atsuo ; Kajihara, Seiji
Author_Institution :
Semicond. Technol. Acad. Res. Center, Yokohama, Japan
Abstract :
In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.
Keywords :
delays; integrated circuit design; integrated circuit testing; statistical analysis; chip defects; chip quality; delay failure; design delay margin; fabrication process quality; marginal delay; statistical delay quality model; test timing accuracy; test vectors; testing cost; Accuracy; Circuit faults; Circuit testing; Clocks; Electronic equipment testing; Fabrication; Predictive models; Process design; Propagation delay; Timing;
Conference_Titel :
Design Automation Conference, 2005. Proceedings of the ASP-DAC 2005. Asia and South Pacific
Print_ISBN :
0-7803-8736-8
DOI :
10.1109/ASPDAC.2005.1466179
